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The SLP74AVC8T245 is an 8-bit transceiver that enables bidirectional level translation. This device uses two separate configurable power-supply rails. Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8V, 1.2V, 1.5V, 1.8V,2.5V and 3.3V). Pins An, OE(——— and DIR are referenced to VCC(A) and pins Bn are referenced to VCC(B).

The SLP74AVC8T245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE(———) input can be used to disable the outputs so the buses are effectively isolated.

The device is fully specified for partial power-down applications using I OFF. The I OFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both An and Bn are in the high-impedance OFF-state.

Main feature

Wide supply voltage range:

VCC(A) : 0.8V to 3.6V

VCC(B) : 0.8V to 3.6V

Suspend mode, Inputs accept voltages up to 3.6V

I OFF circuitry provides partial Power-down mode operation

Maximum data rates:

  • 220Mbit/s (³ 1.8V to 3.3V translation)

  • 180Mbit/s (³ 1.1V to 3.3V translation)

  • 150Mbit/s (³ 1.1V to 2.5V translation)

  • 120Mbit/s (³ 1.1V to 1.8V translation)

  • 100Mbit/s (³ 1.1V to 1.5V translation)

  • 80Mbit/s (³ 1.1V to 1.2V translation)

ESD protection:

  • HBM exceeds 8000V

  • CDM exceeds 1000V

Latch-up performance exceeds 100mA 

Specified from -40°C to +85°C and -40°C to +125°C

Block Diagram


                                                                                              Fig.1 Logic diagram