The SLP74LVC1G125 provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE). The output is disabled when the output-enable (OE)) input is high.
This bus buffer gate is designed for 1.65V to 5.5V VCC operation.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
Supports 1.65V to 5.5V VCC operation
Input accept voltages up to 5V
±24mA output drive (VCC=3.0V)
CMOS low power consumption
HBM exceeds 2000 V
CDM exceeds 1000 V
Latch-up performance exceeds 100 mA
Specified from -40°C to +85°C and from -40°C to +125°C
|Product Name||Package form||Marking||Hazardous Substance Control||Packing Type||Remarks|
|SLP74LVC1G125KMTR||SOT-353-5L||SN||Halogen free||Tape & Reel|
Fig.1 Function diagram
Fig.2 Logic diagram