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The SLP74LVC1G14 is designed for 1.65V to 5.5V VCC operation, provides one inverting buffer.

Inputs can be driven from either 3.3V or 5V devices. These features allow the use of these devices in a mixed 3.3V and 5V system environment.

Schmitt trigger action at the input makes the circuit tolerant for slower input rise and fall time.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing damaging backflow current through the device when it is powered down.

Main feature

Supports 1.65V to 5.5V VCC operation

±24mA output drive at VCC=3.0V

CMOS low power consumption

Direct interface with TTL levels

Input accept voltages up to 5V

ESD protection:

  • HBM Exceeds 2000V

  • CDM Exceeds 1000V

Latch-up performance exceeds 100mA

Specified from -40°C to +85°C and -40°C to +125°C

Block Diagram