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The SLP74GTL2014 is a 4-channel transceiver designed for interface  of LVTTL and GTL-/GTL/GTL+. The transceiver is designed for 3V to 3.6V VCC operation. The LVTTL inputs are tolerant up to 5.5V,  allowing direct access to TTL or CMOS inputs. The device operates as a GTL to LVTTL or LVTTL to GTL translator due to the direction control pin DIR. The reference voltage VREF is adjustable from 0.5V to VCC/2.

The device is specially designed for protect performance during power down using Power-Down-Protect circuit. The Power-Down-Protect circuit disables the output drivers, preventing the damaging outside current back through the device when it is powered down.

Main feature

The LVTTL inputs tolerant to 5.5V

Direct Access to TTL or 5V CMOS

Operates as a GTL to LVTTL or LVTTL to GTL translator 

Adjustable VREF from 0.5V to VCC/2

Partial Power-Down Permitted

ESD protection:

  • HBM exceeds 2000V

  • CDM exceeds 1000V

Latch-up performance exceeds 500mA

Specified from -40°C to +85°C

Block Diagram

SLP74GTL2014   (1440-720).png