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      The SLP74AVC16T245 is an 16-bit, dual supply transceiver that enables bidirectional level translation. It has dual supplies (VCC(A) and VCC(B) ) for voltage translation and four 8-bit input-output ports (nAn and nBn) each with its own output enable (nOE(———) and send/receive (nDIR) input for direction control. VCC(A) and VCC(B) can be independently supplied at any voltage between 0.8V and 3.6V making the device suitable for low voltage translation between any of the following voltages: 0.8V, 1.2V, 1.5V, 1.8V, 2.5V and 3.3V. A HIGH on nDIR selects transmission from nAn to nBn while a LOW on nDIR selects transmission from nBn to nAn. A HIGH on nOE(——— causes the outputs to assume a high-impedance OFF-state. The device control pins (1DIR, 2DIR, /1OE(———, and /2OE(———) are supplied by VCCA.

      The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both An and Bn are in the high-impedance OFF-state.

Main feature
  • Wide supply voltage range

  • VCC(A): 0.8V to 3.6V

  • VCC(B): 0.8V to 3.6V

  • Inputs accept voltages up to 3.6V

  • Control inputs VIH/VIL levels are referenced to VCCA voltage

  • Ioff supports Partial-Power-Down Mode operation

  • Maximum data rates:

  • 220Mbit/s (≥ 1.8V to 3.3V translation)

  • 180Mbit/s (≥ 1.1V to 3.3V translation)

  • 150Mbit/s (≥ 1.1V to 2.5V translation)

  • 120Mbit/s (≥ 1.1V to 1.8V translation)

  • 100Mbit/s (≥ 1.1V to 1.5V translation)

  • 80Mbit/s (≥ 1.1V to 1.2V translation)

  • ESD protection:

  • HBM exceeds 8000V

  • CDM exceeds 1000V

  • Latch-up performance exceeds 100mA

  • Specified from -40°C to +85°C and -40°C to +125°C

Ordering Information
Product Name Package form Marking Hazardous Substance Control Packing Type Remarks
SLP74AVC16T245JZ TSSOP-48-300-0.5 AVC16T245 Halogen free Tube
SLP74AVC16T245JZTR TSSOP-48-300-0.5 AVC16T245 Halogen free Tape&Reel
Block Diagram


                                                                                                Fig.1 Logic diagram