Mailbox verification
Your email:
Verification Code:
Audio Processing SoC With High-Performance DSP

The SC5864A is a highly-integrated audio system-on-chip (SoC) integrated with Cortex-M0 processor for low power management, a high-performance CPU for system control, and a high performance audio dedicated DSP for audio coding/decoding and sound effect processing. Furthermore, it is also integrated with SAR-ADC, USB2.0 controllers, audio CODEC, and I2S audio interface.

Main feature


  • CPU

  • RISC architecture, 32-bit data, 16/32-bit hybrid coding instruction;

  • 3-level pipelines, maximum operating frequency: 160MHz;

  • 32 32-bit general purpose registers, 16 fast interrupt general purpose registers;

  • 16KB cache, four-way set associative, WB/WT supported;

  • Hardware floating-point unit, single-precision floating-point numbers supported;

  • Audio process unit;

  • DSP extended instruction, hardware multiplier, multiplication quickly done in one cycle;

  • Tightly-coupled system IP, including vector interrupt controller and timer;

  • DSP

  • 5-level pipelines, maximum operating frequency: 160MHz;

  • 32bit/16bit multiplication: MAC16, MUL16, MUL32;

  • 32bit integer division;

  • Single-precision floating-point operation;

  • Dedicated hardware audio acceleration engine;

  • 32KB instruction/data Cache, WB/WT supported;

  • Two Local SRAM, 128KB+64KB;

  • Cortex-M0 core

  • High performance 32bit Cortex-M0 core, maximum operating frequency: 80MHz;

  • Embedded 8KB Cache, four address areas, independently configure;

  • Supports frequency reduction, a quarter of maximum bus frequency;

Clock & Power Manager

  • External 12MHz oscillators;

  • Built-in RCL and RCH;

  • Built-in System PLL, Audio PLL and USB1.1 PLL;

  • Built-in double 1.2V LDO;

  • Multi low-power operating modes supported, such as frequency reduction, STOP mode. 

Memory Controller

  • OTP

  • 8KB capacity;

  • Storing startup code, parameters, and key;

  • SPI flash controller

  • Supports SPI Flash 1/2-wire modes;

  • Core runs directly in SPI Flash;

  • SRAM

  • Embedded 240KB SRAM, system 32KB+16KB, DSP 192KB;

  • Supports Byte, Half-word, Word access;

  • SDRAM controller

  • High-efficiency SDRAM Interface, supports 16-bit data operating;

  • Supports SDRAM low-power modes, such as self-refresh, power down, etc.;

  • Packaged with 2MB SDRAM;


  • I2S_I/O

  • I2S_I/O1 supports 5.1 channel, others support 2.0 channel;

  • Supports 24bit@192KHz;

  • Supports clock Master and Slave modes;

  • Supports PDMA mode;

  • Audio CODEC

  • Built-in two-set stereo Audio ADCs; SNR 100db (A-weight, Line in);

  • Supports stereo analog MIC input and ALC;

  • Built-in two-set stereo Audio DAC, SNR 100db(A-weight, Line out);

  • USB_HS

  • Built-in high-speed PHY;

  • Compliance with USB2.0 standard, supports high speed, full speed, and low speed;

  • Supports control, bulk, interrupt, and synchronous transfer;

  • Built-in 2KB SRAM;

  • Built-in Normal and Scatter-Gather DMA transfer;

  • USB_FS

  • Built-in full-speed PHY;

  • Compliance with USB2.0 standard, supports full speed, and low speed;

  • Supports control, bulk, interrupt, and synchronous transfer;

  • Built-in 1KB SRAM;

  • Built-in DMA transfer;


  • Compliance with SD2.0, MMC4.3, and SDIO2.0 standards;

  • Supports 1 and 4-bit modes;

  • Built-in Normal and chained DMA transfer;

  • UARTx3

  • 3 UART modules provided;

  • High-speed UART1 integrated with 64-byte FIFO, UART2 with 8-byte FIFO, while UART3 with 16-byte FIFO;

  • Programmable data bits and stop bit;

  • Parity check supported or no check;

  • Supports receiving/sending FIFO interrupt;

  • PDMA mode supported by UART1;

  • I2C

  • Supports standard speed, fast speed, and high speed modes;

  • Supports Master and Slave modes; 

  • SPI

  • Supports SPI standard 4-wire protocol;

  • Embedded independent 8x32 receive and send buffers;

  • Supports PDMA mode;

  • PWM

  • Supports preset frequency division;

  • 8-channel independent PWM outputs;

  • 16-bit counting accuracy;

  • ADC

  • 6-channel analog inputs, 10bit accuracy; 

  • GPIO

  • Two GPIO controllers;

  • Independent pull-up resistor enable;

  • Selectable drive strength (2/4/8/24mA);

  • Supports configurable interrupt of each IO, edge or level triggered; 

Built-in hardware modules

  • xDMAC

  • Two controllers, supports 12-channel (8+4) independent configurable channels in maximum;

  • Supports Normal and Scatter-Gather transfer modes;

  • Supports Byte-, Half-word-, and Word- access;

  • Supports source/destination address incrementing;

  • Supports 16-channel data request channels;

  • EQ acceleration engine IIR

  • Timer

  • Supports preset frequency division;

  • Five-set independent counters;

  • 32bit counting accuracy;

Block Diagram